diff --git a/mingw-w64-headers/include/winnt.h b/mingw-w64-headers/include/winnt.h
index 5133c1f..9e660bc 100644
--- a/mingw-w64-headers/include/winnt.h
+++ b/mingw-w64-headers/include/winnt.h
@@ -4180,6 +4180,44 @@
       PVOID UmsCompletionList;
     } UMS_CREATE_THREAD_ATTRIBUTES,*PUMS_CREATE_THREAD_ATTRIBUTES;
 
+#define COMPONENT_KTM 0x01
+#define COMPONENT_VALID_FLAGS COMPONENT_KTM
+
+    typedef struct _COMPONENT_FILTER {
+      DWORD ComponentFlags;
+    } COMPONENT_FILTER,*PCOMPONENT_FILTER;
+
+#define DYNAMIC_EH_CONTINUATION_TARGET_ADD 0x00000001
+#define DYNAMIC_EH_CONTINUATION_TARGET_PROCESSED 0x00000002
+
+    typedef struct _PROCESS_DYNAMIC_EH_CONTINUATION_TARGET {
+      ULONG_PTR TargetAddress;
+      ULONG_PTR Flags;
+    } PROCESS_DYNAMIC_EH_CONTINUATION_TARGET,*PPROCESS_DYNAMIC_EH_CONTINUATION_TARGET;
+
+    typedef struct _PROCESS_DYNAMIC_EH_CONTINUATION_TARGETS_INFORMATION {
+      WORD NumberOfTargets;
+      WORD Reserved;
+      DWORD Reserved2;
+      PPROCESS_DYNAMIC_EH_CONTINUATION_TARGET Targets;
+    } PROCESS_DYNAMIC_EH_CONTINUATION_TARGETS_INFORMATION,*PPROCESS_DYNAMIC_EH_CONTINUATION_TARGETS_INFORMATION;
+
+#define DYNAMIC_ENFORCED_ADDRESS_RANGE_ADD 0x00000001
+#define DYNAMIC_ENFORCED_ADDRESS_RANGE_PROCESSED 0x00000002
+
+    typedef struct _PROCESS_DYNAMIC_ENFORCED_ADDRESS_RANGE {
+      ULONG_PTR BaseAddress;
+      SIZE_T Size;
+      DWORD Flags;
+    } PROCESS_DYNAMIC_ENFORCED_ADDRESS_RANGE,*PPROCESS_DYNAMIC_ENFORCED_ADDRESS_RANGE;
+
+    typedef struct _PROCESS_DYNAMIC_ENFORCED_ADDRESS_RANGES_INFORMATION {
+      WORD NumberOfRanges;
+      WORD Reserved;
+      DWORD Reserved2;
+      PPROCESS_DYNAMIC_ENFORCED_ADDRESS_RANGE Ranges;
+    } PROCESS_DYNAMIC_ENFORCED_ADDRESS_RANGES_INFORMATION,*PPROCESS_DYNAMIC_ENFORCED_ADDRESS_RANGES_INFORMATION;
+
     typedef struct _QUOTA_LIMITS {
       SIZE_T PagedPoolLimit;
       SIZE_T NonPagedPoolLimit;
@@ -4252,6 +4290,8 @@
       ProcessPayloadRestrictionPolicy,
       ProcessChildProcessPolicy,
       ProcessSideChannelIsolationPolicy,
+      ProcessUserShadowStackPolicy,
+      ProcessRedirectionTrustPolicy,
       MaxProcessMitigationPolicy
     } PROCESS_MITIGATION_POLICY,*PPROCESS_MITIGATION_POLICY;
 
@@ -4426,6 +4466,36 @@
       };
     } PROCESS_MITIGATION_SIDE_CHANNEL_ISOLATION_POLICY, *PPROCESS_MITIGATION_SIDE_CHANNEL_ISOLATION_POLICY;
 
+    typedef struct _PROCESS_MITIGATION_USER_SHADOW_STACK_POLICY {
+      __C89_NAMELESS union {
+        DWORD Flags;
+        __C89_NAMELESS struct {
+          DWORD EnableUserShadowStack : 1;
+          DWORD AuditUserShadowStack : 1;
+          DWORD SetContextIpValidation : 1;
+          DWORD AuditSetContextIpValidation : 1;
+          DWORD EnableUserShadowStackStrictMode : 1;
+          DWORD BlockNonCetBinaries : 1;
+          DWORD BlockNonCetBinariesNonEhcont : 1;
+          DWORD AuditBlockNonCetBinaries : 1;
+          DWORD CetDynamicApisOutOfProcOnly : 1;
+          DWORD SetContextIpValidationRelaxedMode : 1;
+          DWORD ReservedFlags : 22;
+        };
+      };
+    } PROCESS_MITIGATION_USER_SHADOW_STACK_POLICY, *PPROCESS_MITIGATION_USER_SHADOW_STACK_POLICY;
+
+    typedef struct _PROCESS_MITIGATION_REDIRECTION_TRUST_POLICY {
+      __C89_NAMELESS union {
+        DWORD Flags;
+        __C89_NAMELESS struct {
+          DWORD EnforceRedirectionTrust : 1;
+          DWORD AuditRedirectionTrust : 1;
+          DWORD ReservedFlags : 30;
+        };
+      };
+    } PROCESS_MITIGATION_REDIRECTION_TRUST_POLICY, *PPROCESS_MITIGATION_REDIRECTION_TRUST_POLICY;
+
     typedef struct _JOBOBJECT_BASIC_ACCOUNTING_INFORMATION {
       LARGE_INTEGER TotalUserTime;
       LARGE_INTEGER TotalKernelTime;
@@ -4758,6 +4828,16 @@
       DWORD64 CycleTime;
     } SYSTEM_PROCESSOR_CYCLE_TIME_INFORMATION,*PSYSTEM_PROCESSOR_CYCLE_TIME_INFORMATION;
 
+    typedef struct _SYSTEM_SUPPORTED_PROCESSOR_ARCHITECTURES_INFORMATION {
+      DWORD Machine : 16;
+      DWORD KernelMode : 1;
+      DWORD UserMode : 1;
+      DWORD Native : 1;
+      DWORD Process : 1;
+      DWORD WoW64Container : 1;
+      DWORD ReservedZero0 : 11;
+    } SYSTEM_SUPPORTED_PROCESSOR_ARCHITECTURES_INFORMATION,*PSYSTEM_SUPPORTED_PROCESSOR_ARCHITECTURES_INFORMATION;
+
 #define PROCESSOR_INTEL_386 386
 #define PROCESSOR_INTEL_486 486
 #define PROCESSOR_INTEL_PENTIUM 586
@@ -4834,19 +4914,58 @@
 #define PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE 31
 #define PF_RDTSCP_INSTRUCTION_AVAILABLE 32
 #define PF_RDPID_INSTRUCTION_AVAILABLE 33
+#define PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE 34
+#define PF_MONITORX_INSTRUCTION_AVAILABLE 35
+#define PF_SSSE3_INSTRUCTIONS_AVAILABLE 36
+#define PF_SSE4_1_INSTRUCTIONS_AVAILABLE 37
+#define PF_SSE4_2_INSTRUCTIONS_AVAILABLE 38
+#define PF_AVX_INSTRUCTIONS_AVAILABLE 39
+#define PF_AVX2_INSTRUCTIONS_AVAILABLE 40
+#define PF_AVX512F_INSTRUCTIONS_AVAILABLE 41
+#define PF_ERMS_AVAILABLE 42
+#define PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE 43
+#define PF_ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE 44
 
 #define XSTATE_LEGACY_FLOATING_POINT (0)
 #define XSTATE_LEGACY_SSE (1)
 #define XSTATE_GSSE (2)
 #define XSTATE_AVX (XSTATE_GSSE)
+#define XSTATE_MPX_BNDREGS (3)
+#define XSTATE_MPX_BNDCSR (4)
+#define XSTATE_AVX512_KMASK (5)
+#define XSTATE_AVX512_ZMM_H (6)
+#define XSTATE_AVX512_ZMM (7)
+#define XSTATE_IPT (8)
+#define XSTATE_PASID (10)
+#define XSTATE_CET_U (11)
+#define XSTATE_CET_S (12)
+#define XSTATE_AMX_TILE_CONFIG (17)
+#define XSTATE_AMX_TILE_DATA (18)
+#define XSTATE_LWP (62)
+#define MAXIMUM_XSTATE_FEATURES (64)
 
 #define XSTATE_MASK_LEGACY_FLOATING_POINT (1ULL << (XSTATE_LEGACY_FLOATING_POINT))
 #define XSTATE_MASK_LEGACY_SSE (1ULL << (XSTATE_LEGACY_SSE))
 #define XSTATE_MASK_LEGACY (XSTATE_MASK_LEGACY_FLOATING_POINT | XSTATE_MASK_LEGACY_SSE)
 #define XSTATE_MASK_GSSE (1LLU << (XSTATE_GSSE))
 #define XSTATE_MASK_AVX (XSTATE_MASK_GSSE)
-
-#define MAXIMUM_XSTATE_FEATURES (64)
+#define XSTATE_MASK_MPX ((1LLU << (XSTATE_MPX_BNDREGS)) | (1LLU << (XSTATE_MPX_BNDCSR)))
+#define XSTATE_MASK_AVX512 ((1LLU << (XSTATE_AVX512_KMASK)) | (1LLU << (XSTATE_AVX512_ZMM_H)) | (1LLU << (XSTATE_AVX512_ZMM)))
+#define XSTATE_MASK_IPT (1LLU << (XSTATE_IPT))
+#define XSTATE_MASK_PASID (1LLU << (XSTATE_PASID))
+#define XSTATE_MASK_CET_U (1LLU << (XSTATE_CET_U))
+#define XSTATE_MASK_CET_S (1LLU << (XSTATE_CET_S))
+#define XSTATE_MASK_AMX_TILE_CONFIG (1LLU << (XSTATE_AMX_TILE_CONFIG))
+#define XSTATE_MASK_AMX_TILE_DATA (1LLU << (XSTATE_AMX_TILE_DATA))
+#define XSTATE_MASK_LWP (1LLU << (XSTATE_LWP))
+#if defined(_AMD64_) || defined(__x86_64__)
+#define XSTATE_MASK_ALLOWED (XSTATE_MASK_LEGACY | XSTATE_MASK_AVX | XSTATE_MASK_MPX | XSTATE_MASK_AVX512 | XSTATE_MASK_IPT | XSTATE_MASK_PASID | XSTATE_MASK_CET_U | XSTATE_MASK_AMX_TILE_CONFIG | XSTATE_MASK_AMX_TILE_DATA | XSTATE_MASK_LWP)
+#elif defined(_X86_) || defined(__i386__)
+#define XSTATE_MASK_ALLOWED (XSTATE_MASK_LEGACY | XSTATE_MASK_AVX | XSTATE_MASK_MPX | XSTATE_MASK_AVX512 | XSTATE_MASK_IPT | XSTATE_MASK_CET_U | XSTATE_MASK_LWP)
+#endif
+#define XSTATE_MASK_PERSISTENT ((1LLU << (XSTATE_MPX_BNDCSR)) | XSTATE_MASK_LWP)
+#define XSTATE_MASK_USER_VISIBLE_SUPERVISOR (XSTATE_MASK_CET_U)
+#define XSTATE_MASK_LARGE_FEATURES (XSTATE_MASK_AMX_TILE_DATA)
 
     typedef struct _XSTATE_FEATURE {
       DWORD Offset;